您的瀏覽器不支援Javascript,部分功能將無法呈現。

:::

Research

:::
Project
Project typeResearch Projects
Year2018
Project NameTheoretical Design and FPGA Circuit Implementation of Iterative Learning Controller for Consideration of both Learning Performance and Memory Capacity
Period2018-08 ~ 2019-07
ParticipatorChiang-Ju Chien
Job TitlePrincipal Investigator
Funding institutionsMinistry of Science and Technology, Taiwan
NoteMOST107-2221-E-211-005
裝飾性圖片
cron web_use_log